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january 2000 revision 4.0 1 psx family data sheet f eatures ? sram-based, in-system programmable ? switch matrix non-blocking programmable bus widths of 4, 8, 16 and 32 bits identical and predictable delays one-to-one, one-to-many and many-to-one connections ? rapidconnect? parallel interface for fast, incremental switching of buses in 12.5 ns bank switching for instantaneous reconfiguration of entire switch matrix ? clocked, latched and flow-through dataflow modes as low as 7.0ns pin-to-pin delay in flow-through mode and 133mhz clock rate in registered mode. ? i/o ports individually programmable as input, output or bidirectional for each i/o port, clock, clock enable, input enable and output enable can be selected independently from a large pool of common control signals 16 ma current drive separated i/o power pins for easy interfacing between 5v and 3.3v signals. d escription the psx160, psx128b and psx96b are sram-based bus oriented switches with 160, 128 and 96 i/os respectively. the devices are manufactured using a 0.6 m cmos process and can be clocked up to 133 mhz. the psx devices are used in applications requiring dynamic switching, such as communication switches, network hubs and routers, image processing engines, file/video servers and multiprocessing shared-memory systems. at the heart of psx devices is a non-blocking switch matrix. the lines in the switch matrix can be grouped and controlled as 4, 8, 16 or 32 signal busses. any bus can be connected to one or more other busses. the switch matrix lines are connected to i/o ports whose functional attributes are programmable. the rapidconnect parallel interface allows connections in the switch matrix to be changed quickly and incrementally. in addition, the dual configuration memory banks allow a new switch configuration to be loaded in the inactive bank and swap it in instantaneously. in either case, data integrity is maintained on all unchanged connections. the psx devices support an industry standard jtag (ieee 1149.1) interface for boundary scan testing. the same interface is also used for downloading the configuration bit stream into the psx devices. figure 1. psx functional block diagram general control rapid- connect interface hierarchical switch matrix jtag configuration control prog. i/o buffer prog. i/o buffer prog. i/o buffer tdi tms tck tdo address key control data control p000 p001 pnnn i/o control bank select
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contents january 2000 revision 4.0 3 features ....................................................................................................................... .................................1 description.................................................................................................................... ...............................1 1.0 architecture .............................................................................................................. ............................9 1.1 hierarchical, dual-bank switch matrix..................................................................................... .....9 1.1.1 hierarchical control structure.......................................................................................... .....9 1.1.2 switching of 4-bit buses ................................................................................................ .....10 1.1.3 switching of 8-bit buses ................................................................................................ .....10 1.1.4 switching of 16 and 32-bit buses .......................................................................................1 0 1.1.5 level-1 configuration................................................................................................... .......10 1.1.6 i/o port grouping ....................................................................................................... .........10 1.1.7 dual banks.............................................................................................................. .............10 1.2 programmable i/o port ..................................................................................................... ............11 1.2.1 i/o port functional modes ............................................................................................... ...11 1.2.2 pin and array side trickle current...................................................................................... 15 1.2.3 programmable pull-up current ............................................................................................ 15 1.3 i/o control signals ....................................................................................................... ................15 1.3.1 general control......................................................................................................... ...........15 1.3.2 key controls ............................................................................................................ ............15 1.4 i/o port assignment for nibble, byte, word and long word groups ........................................16 1.5 rapidconnect switching interface .......................................................................................... .....17 1.6 jtag-based configuration controller ....................................................................................... ..17 1.6.1 jtag interface .......................................................................................................... ..........17 1.6.2 i/o port configuration .................................................................................................. .......18 1.6.3 switch matrix configuration ............................................................................................. ..18 1.6.4 mode control register configuration .................................................................................18 2.0 miscellaneous details ..................................................................................................... ....................18 2.1 device reset .............................................................................................................. ...................18 2.2 mode control register..................................................................................................... .............18 2.3 mixed voltage operation ................................................................................................... ..........18 3.0 rapidconnect address computation.......................................................................................... ........19 4.0 in system configuration using jtag-based configuration controller ............................................20 4.1 bit stream generation ..................................................................................................... .............20 4.2 bit stream downloading .................................................................................................... ..........20 5.0 configuration time and bit stream size.................................................................................... ........22 5.1 configuring multiple psx devices .......................................................................................... ....22 6.0 pin summary............................................................................................................... ........................23 7.0 electrical specifications ................................................................................................. ....................24 7.1 absolute maximum rating (1) ......................................................................................................24 7.2 recommended operating conditions (2) ...................................................................................24 7.3 capacitance (3) ..............................................................................................................................2 4 7.4 dc electrical specifications .............................................................................................. ...........25
contents 4 revision 4.0 january 2000 7.5 ac electrical specifications .............................................................................................. ...........26 7.6 parameter de-rating for one-to-many connections....................................................................28 7.7 test circuit and timing diagrams .......................................................................................... .....29 7.8 external ac timing characteristics as functions of internal ac timing characteristics..........35 7.9 internal ac timing characteristics for -133 speed grade (all times are in ns)...........................36 7.10 circuit models for internal timing ....................................................................................... .....37 7.11 typical ac and dc characteristics........................................................................................ ....39 8.0 pinout .................................................................................................................... ..............................40 8.1 psx160 [pqfp 240l package] pinout by pin location ..............................................................40 8.2 psx160 [pqfp 240l package] pinout by pin name ..................................................................41 8.3 psx160 [pqfp 240l package] pinout......................................................................................... 42 8.4 psx128b [pqfp 208l package] pinout by pin location ...........................................................43 8.5 psx128b [pqfp 208l package] pinout by pin name ................................................................44 8.6 psx128b [pqfp 208l package] pinout ......................................................................................45 8.7 psx96b [pqfp 160l package] pinout by pin location ......................................................... 46 8.8 psx96b [pqfp 160l package] pinout by pin name .................................................................47 8.9 psx96b [pqfp 160l package] pinout ........................................................................................4 8 9.0 mechanical specification.................................................................................................. ..................49 9.1 pqfp package dimensions ................................................................................................... .......49 10.0 package thermal resistance............................................................................................... ..............50 11.0 component availability and ordering information .........................................................................5 1 12.0 psx family at a glance................................................................................................... .................52 13.0 product status definitions ............................................................................................... .................53
tables january 2000 revision 4.0 5 table 1. summary of programmable i/o attributes for psx devices.....................................................12 table 2. i/o port assignment for nibble, byte, word and long word...................................................16 table 3. making/breaking a connection ......................................................................................... .........19 table 4. number of jtag cycles and configuration time (using a 10 mhz jtag clock) ..................22 table 5. psx pin summary ...................................................................................................... ................23 table 6. supply voltage source ................................................................................................ ...............23 table 7. absolute maximum ratings ............................................................................................. ..........24 table 8. recommended operating conditions..................................................................................... ....24 table 9. capacitance.......................................................................................................... .......................24 table 10. dc electrical specification ......................................................................................... .............25 table 11. ac electrical specifications........................................................................................ .............26 table 12. parameter de-rating for one-to-many connections................................................................28 table 13. external ac timing characteristics.................................................................................. .......35 table 14. internal ac timing characteristics.................................................................................. ........36 table 15. psx160 [pqfp 240l package] pinout by pin location ..........................................................40 table 16. psx160 [pqfp 240l package] pinout by pin name...............................................................41 table 17. psx128b [pqfp 208l package] pinout by pin location .......................................................43 table 18. psx128b [pqfp 208l package] pinout by pin name ............................................................44 table 19. psx96b [pqfp 160l package] pinout by pin location .........................................................46 table 20. psx96b [pqfp 160l package] pinout by pin name ..............................................................47 table 21. pqfp package dimensions ............................................................................................. .........49 table 22. thermal resistance of psx packages .................................................................................. ....50 table 23. component availability.............................................................................................. ..............51 table 24. ordering information................................................................................................ ................51 table 25. psx family summary .................................................................................................. ............52
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figures january 2000 revision 4.0 7 figure 1. psx functional block diagram ........................................................................................ ..........1 figure 2. switch matrix and nibble switch ..................................................................................... ..........9 figure 3. two level sram cell structure (8 x 8 section of switch matrix is shown)............................9 figure 4. sram clusters for wider bus switching ............................................................................... .10 figure 5. level-1 sram cell data for 8 and 16-bit buses (can be extended to 32-bits).........................10 figure 6. switch matrix control............................................................................................... ................11 figure 7. programmable i/o port buffer ........................................................................................ ..........11 figure 8. psx output driver and pull-up current ............................................................................... ...15 figure 9. i/o control ......................................................................................................... .......................15 figure 10. psx rapidconnect system interface.................................................................................. ....17 figure 11. reset circuit ...................................................................................................... ......................18 figure 12. off-line bit stream generation ..................................................................................... ..........20 figure 13. embedded bit stream generation ..................................................................................... ......20 figure 14. configuring multiple psx devices ................................................................................... .....22 figure 15. test circuit and waveform definition............................................................................... .....29 figure 16. registered input and registered output mode timing (iclk/oclk synchronized) ..........29 figure 17. registered input mode timing ....................................................................................... ........29 figure 18. registered output mode timing...................................................................................... .......30 figure 19. i/o port timing (flow-through mode) ................................................................................ ...30 figure 20. output enable timing (flow-through mode) .........................................................................30 figure 21. input enable timing (flow-through mode)............................................................................ 31 figure 22. latched input mode timing.......................................................................................... ..........31 figure 23. latched output mode timing ......................................................................................... ........31 figure 24. key timing for register input, clock enable (cke).............................................................32 figure 25. key timing for register output, clock enable (cke) ..........................................................32 figure 26. key timing for output enable....................................................................................... .........32 figure 27. key timing for input enable ........................................................................................ ..........33 figure 28. key timing for latch input, enable (cke)........................................................................... .33 figure 29. key timing for latch output, enable (cke) .........................................................................3 3 figure 30. rapidconnect timing ................................................................................................ .............34 figure 31. jtag timing ........................................................................................................ ..................34 figure 32. internal timing model 1: flow through (from input to switch matrix) ...............................37 figure 33. internal timing model 2: flow through (from switch matrix to output) ............................37 figure 34. internal timing model 3: latched input (from input to switch matrix) ................................37 figure 35. internal timing model 4: latched output (from switch matrix to output)..........................37 figure 36. internal timing model 5: registered input (from input to switch matrix)............................38 figure 37. internal timing model 6: registered output (from switch matrix to output) .....................38 figure 38. internal timing model 7: switch matrix delay when switching banks ................................38 figure 39. internal timing model 8: switch matrix delay......................................................................3 8 figure 40. psx160 [pqfp 240l package] pinout .................................................................................. .42 figure 41. psx128b [pqfp 208l package] pinout................................................................................. 45
figures 8 revision 4.0 january 2000 figure 42. psx96b [pqfp 160l package] pinout.................................................................................. .48 figure 43. pqfp package dimensions ............................................................................................ .........49
psx family data sheet january 2000 revision 4.0 9 1.0 a rchitecture psx devices are sram-based bus-oriented switching matrices. the devices can be configured and controlled in-system by storing appropriate data into the internal sram cells and configuration registers. the main functional blocks of the device are the hierarchical, dual-bank switch matrix, programmable i/o ports, i/o control signal block, rapidconnect switching interface and a jtag-based configuration controller. the full-featured programmable i/o ports are grouped into 4 (i. e. nibbles) for the purpose of switching. they can be further grouped into 8 (2 nibbles), 16 (4 nibbles) or 32-bit (8 nibbles) groups for byte, word and long word buses respectively. these port groups and their associated signal lines can be connected internally to other buses using the switch matrix. the i/o port control signals such as clock, clock enable, input enable, and output enable are used to control the flow of data through the i/o ports. the jtag-based serial configuration controller is used to configure the i/o ports and switch matrix sram cells, thereby establishing the desired functional attributes for the i/o ports and connections among them through the switch matrix. the rapidconnect interface is used to directly address the sram cells controlling the switches allowing connections to be changed with a single write operation. 1.1 hierarchical, dual-bank switch matrix the switch matrix is an x-y routing structure (or grid). each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots in figure 2. an i/o port pin connects to this horizontal-vertical trace pair through a programmable buffer. the psx switch matrix has a nibble or 4- bit granularity; i.e. the wires in the switch matrix are combined as 4-bit buses or nibbles and switched as groups. signal paths through the switch matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. figure 2. switch matrix and nibble switch at the intersection of unique nibble buses are four pass transistors with a common control. these pass transistors allow a one-to-one connection of the corresponding bits between two nibbles (i.e., bit_0 in nibble i and bit_0 in nibble j). bits within a nibble (i.e., bit_0 and bit_1 in nibble i) cannot be connected. similarly, non-corresponding bits between the nibbles (i.e., bit_0 in nibble i and bit_2 in nibble j) cannot be connected either. multicasting/broadcasting operation is supported by allowing one nibble to be connected to multiple other nibbles. 1.1.1 hierarchical control structure the pass transistors are controlled by a hierarchical (two-level) sram cell structure as shown in figure 3. the two level structure allows the psx device to switch 4-bit buses or 8, 16, 32-bit buses. to activate (turn on) a group of 4 switches (nibble), two sram cells, one at level 1 and one at level 2 must be set. notice from the figure that a level-2 sram cell is common to two 4-bit buses, and therefore controls an 8-bit bus. figure 3. two level sram cell structure (8 x 8 section of switch matrix is shown) control i.0 i.1 i.2 i.3 j.0 j.1 j.2 j.3 0 1 i j 2 3 4 5 6 7 0 1 2 3 4 5 6 7 level 1 sram cell level 2 sram cell
psx family data sheet 10 revision 4.0 january 2000 1.1.2 switching of 4-bit buses switching of 4-bit buses is achieved by first setting the corresponding level-2 sram cell (statically, or during device initialization), and then writing to the appropriate level-1 sram cell(s) to make or break connections. if all i/o ports are used for 4-bit switching, then all level-2 sram cells are set to 1. 1.1.3 switching of 8-bit buses switching of 8-bit buses is achieved by first setting the appropriate level-1 sram cells (statically, or during device initialization; see section level 1 configuration), and then writing to the appropriate level-2 sram cell to make or break an 8-bit bus connection. notice from figure 4 that four (2 x 2) level- 1 sram cells must be initialized to facilitate the switching of two 8-bit buses. 1.1.4 switching of 16 and 32-bit buses this is conceptually similar to switching of 8-bit buses. it is accomplished by first setting the appropriate level-1 sram cells (statically, or during device initialization), and then writing to multiple level-2 sram cells to make or break a 16 or 32-bit bus connection. the rapidconnect switching interface, described in detail later, allows changing the contents of multiple level-2 sram cells simultaneously. the multiple level 2 sram cells are clustered as shown in figure 4. a 2 x 2 cluster of level-2 sram cells is simultaneously written (with the same data) to effect 16- bit switching, while a 4 x 4 cluster of level-2 sram cells is simultaneously written (with the same data) to effect 32-bit switching. notice from figure 4 that 16 (4 x 4) and 64 (8 x 8) level-1 sram cells must be initialized to facilitate the switching of two 16-bit and 32-bit buses respectively. figure 4. sram clusters for wider bus switching 1.1.5 level-1 configuration in order to perform switching of 8, 16 and 32-bit buses, level 1 sram cells must first be initialized. for each 8-bit switch, four (2 x 2) level 1 sram cells must be programmed. for each 16-bit switch, sixteen (4 x 4) level 1 sram cells must be programmed and for each 32-bit switch, 64 (8 x 8) level 1 sram cells must be programmed. the typical level 1 bit pattern is 1s along the diagonal and 0s in the remaining sram cells. figure 5 illustrates some patterns for byte and word switching. the same concepts can be applied to 32-bit switching. figure 5. level-1 sram cell data for 8 and 16-bit buses (can be extended to 32-bits) for proper operation, no more than one level-1 sram cell should be set for each cluster row. likewise, no more than one level-1 sram cell should be set for each cluster column. as shown in the figure, normal bus switching is achieved with a diagonal pattern. bus swapping is achieved with an offset striped diagonal pattern. any swapping pattern is permitted as long as the one cell per cluster row and one cell per cluster column rule is followed. 1.1.6 i/o port grouping i/o ports are grouped in a predefined manner to form buses. i/o ports for a given bus must be contiguous and as specified in section i/o port assignment for nibble, byte, word and long word groups. 1.1.7 dual banks the psx family provides dual sram to an entirely new switch matrix configuration instantaneously. as shown in figure 6 the on/off control for the pass transistors in the switch matrix is derived by multiplexing the data from two sram cells belonging to bank 0 and bank 1. a bank select pin on the device selects the controlling or active sram bank. the contents of the other ( inactive ) bank can be changed using the rapidconnect interface, described later, without affecting the switch matrix 8-bit bus 16-bit bus 32-bit bus level-2 level-1 level 2 sram cell level 1 sram cell 0 1 03 8-bit bus normal swapped nibbles swapped bytes word connections byte connections 8-bit bus 0 4 4 3 70347 7 1 0 1 0 0 3 4 7 0 1 0 0 03 16-bit bus normal 16-bit bus 0 3 47 12 8 11 4 7 8111215 15 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 03 0 3 47 12 8 11 4 7 8111215 15 1 0 0 0 0 0 0 0 0 0 0 1 1 0
psx family data sheet january 2000 revision 4.0 11 configuration that is active. when the required changes to the inactive bank are completed, the bank select pin can be used to toggle the active bank. figure 6. switch matrix control note that the contents of the active bank can also be changed using either the rapidconnect or the jtag interfaces. in doing so the switch matrix connections change as soon as the configuration data is written to the sram cells. the integrity of other connections defined by the active bank are not affected. this is useful when the switch matrix connections are changed one at a time. 1.2 programmable i/o port each signal line in the switch matrix is connected to a programmable i/o port. the functional attributes of i/o ports are individually programmable. the i/o port attributes include its signal direction (in, out or bidirectional), data flow mode (flow through, registered or latched), and pull-up current. figure 7 shows the structure of the programmable i/o port for psx. also programmable are the sources for the four control signals: clock, clock enable, input enable, and output enable. the sources of these control signals are later described in the section on i/o control signals. figure 7. programmable i/o port buffer 1.2.1 i/o port functional modes table 1 describes the various modes of the i/o port and the mnemonic used by i-cube development system software. signals a x and p x in the table refer to the switch matrix (array) line and i/o port pin respectively. legend: a x - switch matrix signal p x - i/o port pin signal ie - input enable oe - output enable clk - clock cke - clock enable nibble i nibble j 4 4 j .2 j .1 j .0 i .3 i .2 i .1 i .0 j .3 level 1 sram cells bank select on/off control bank 1 bank 0 1 0 level 2 sram cells i/o port br delay nb clk cke ie oe reg lat reg e e e e lat switch matrix ck ck nc nc
psx family data sheet 12 revision 4.0 january 2000 symbol i/o port function mnemonic input - the external signal is buffered from the i/o port pin to the corresponding switch matrix line. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. in registered input - the external signal at the i/o port pin is registered by an edge- triggered flip-flop within the i/o port. a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) and input enable (ie) are also available but not required. either polarity can be selected for ie and cke. the default level for ie and cke is a logic 1. the output of the flip-flop is unknown after hardware reset (trst* = 0). ri latched input - the external signal at the i/o port pin is latched by a level-sensitive flip- flop within the i/o port. a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. an input enable (ie) is also available but not required. either polarity can be selected for clk, cke and ie. the default level for all three is a logic 1. the output of the flip-flop is unknown after hardware reset (trst* = 0). li output - the internal signal is buffered from the corresponding switch matrix line to the i/o port pin. in this mode an optional output enable (oe) can be selected. either polarity can be selected for oe. the default level is a logic 0. op registered output - the internal signal on the switch matrix line is registered by an edge- triggered flip-flop within the i/o port. a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) and output enable (oe) are also available but not required. either polarity can be selected for cke and oe. the default level for cke is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). ro latched output - the internal signal on the switch matrix line is latched by a level- sensitive flip-flop within the i/o port. a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. an output enable (oe) is also available but not required. either polarity can be selected for clk and cke. the default level for both is a logic 1. either polarity can be selected for oe. the default level is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). lo bidirectional transceiver - in this mode, the i/o buffer acts as a bidirectional transceiver between the i/o port pin and the corresponding switch matrix line. this mode requires an input enable (ie) and output enable (oe). either polarity can be selected for each but the default level for ie is a logic 1 and the default level for oe is a logic 0. when the same source (with default polarities) is used for ie and oe, it effectively acts as a direction control. when the same control signal (with one polarity inverted) is used for ie and oe, it effectively acts as a bus repeater (br) (see below) when both are enabled, and as no connect (nc) when neither is enabled. bt bidirectional transceiver with registered input - this mode combines registered input (ri) and output buffer (op). a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) is available but not required. either polarity can be selected. the default level for cke is a logic 1. this mode also requires an input enable (ie) and output enable (oe). either polarity can be selected for each. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&ri table 1. summary of programmable i/o attributes for psx devices px ax ie d ce q cke clk px ax ie d le q cke clk px ax ie px ax oe d ce q cke clk px ax oe d le q cke clk px ax oe px ax ie oe ie px ax oe ce cke clk dq
psx family data sheet january 2000 revision 4.0 13 bidirectional transceiver with latched input - this mode combines latched input (li) and output buffer (op). a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. either polarity can be selected for clk and cke. the default level for both is a logic 1. this mode also requires an input enable (ie) and output enable (oe). either polarity can be selected for ie and oe. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&li bidirectional transceiver with registered output - this mode combines registered output (ro) and input buffer (in). a clock source is required in this mode. either edge of clk can be selected although the default is rising edge. a clock enable (cke) is available but not required. either polarity can be selected but the default level is a logic 1. this mode also requires an input enable (ie) and output enable (oe). either polarity can be selected for ie and oe. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&ro bidirectional transceiver with latched output - this mode combines latched output (lo) and input buffer (in). a latch enable source is required in this mode. the latch enable source is composed of clk and cke. a t least one must be specified. either polarity can be selected for clk and cke. the default level for both is a logic 1. this mode also requires an input enable (ie) and output enable (oe). either polarity can be selected for ie and oe. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&lo bidirectional transceiver with registered i/o - this mode is a combination of registered input (ri) and registered output (ro). a clock source is required in this mode. either edge of clk can be selected. the default is rising edge. a clock enable (cke) is available but not required. either polarity can be selected for cke. the default level is a logic 1. this mode also requires an input enable (ie) and output enable (oe). either polarity can be selected for ie and oe. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flops is unknown after hardware reset (trst* = 0). bt&ri&ro other bt modes - other combinations of i/o port modes (not covered in this table) are less likely but can be used. the mnemonic is bt [&ri | &li] [&ro | &lo], where the specification inside the brackets [ ] is optional and | stands for either or. insure that control signal requirements are met. in these modes, the output of the flip-flops is unknown after hardware reset (trst* = 0). bus repeater - in the bus repeater mode, the i/o port behaves as a wire (with a non- zero propagation delay). this unique feature (patented by i-cube) incorporates a self- sensing circuit to determine signal direction and does not require a direction control signal. when multiple i/o ports, configured as bus repeater, are connected together through the switch matrix to form a single internal node, a signal appearing at any one of the i/o ports gets repeated (or broadcast) to other i/o ports. the bus repeater mode requires a pull-up current source (see section on programmable pull-up current) to operate properly. for more details, refer to the technical note: the bus repeater mode. br array side force 0 - in this input mode, the switch matrix line is forced low (logic 0), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. a0 symbol i/o port function mnemonic table 1. summary of programmable i/o attributes for psx devices (continued) d le q cke clk ie px ax oe px ax ie oe ce cke clk dq d le q cke clk px ax ie oe d q cke ce clk q d px ax ie oe px ax px ax
psx family data sheet 14 revision 4.0 january 2000 array side force 1 - in this input mode, the switch matrix line is forced high (logic 1), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. a1 pin side force 0 - in this output mode, the i/o port pin is forced low (logic 0), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe) can be selected. either polarity can be selected for oe. the default level is a logic 0. f0 pin side force 1 - in this output mode, the i/o port pin is forced high (logic 1), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe) can be selected. either polarity can be selected for oe. the default level is a logic 0. f1 non-buffered - in this mode, the i/o port pin is directly connected to the corresponding line in the switch matrix through a pass transistor, bypassing the buffer. this mode is not controlled by any of the four control signals (clk, cke, ie, and oe) and is not used for passing digital signals. nb no connect - in this mode, the i/o port pin is isolated from the switch matrix. this is done by tristating both the input and output part of the i/o buffer. upon hardware reset (trst* = 0), all i/o ports are automatically configured in this mode no connect (nc). nc symbol i/o port function mnemonic table 1. summary of programmable i/o attributes for psx devices (continued) px ax ie px ax oe px ax px ax px ax
psx family data sheet january 2000 revision 4.0 15 1.2.2 pin and array side trickle current n-channel devices are used as a trickle current source (nominally 10 a) i pt , on the pin side and switch matrix side for each i/o port. upon reset, these current sources are turned on. they can be turned off by configuring the i/o port to do so. 1.2.3 programmable pull-up current as shown in figure 8, the i/o port contains several pull-up devices. the normal pull-up current is supplied by an n-channel device which is controlled by internally generated control signals. figure 8. psx output driver and pull-up current an additional static pull-up current (i pu-wk ) or (i pu-sg ) can be programmed at each i/o port pin. this additional pull-up current is primarily used for the bus repeater (br) mode, but its use is not restricted to that mode alone. 1.3 i/o control signals the psx family has a flexible control structure that gives the user complete control over the behavior of each i/o port. as shown in figure 9 and described below, clock (clk), clock enable (cke), input enable (ie) and output enable (oe) for each i/o port can be selected from two different sets of control inputs. the control polarity can be individually selected. figure 9. i/o control 1.3.1 general control i/o ports can be individually programmed to use a signal from a large pool of dedicated control pins called general control (gcx) on the device. 1.3.2 key controls each i/o port contains a 5-bit tag which can be programmed with a unique value. a comparator in each i/o port continually compares the assigned tag value with the signals present on the key control pins. the output of the comparator, which produces a logic 1 on a match, can be selected as a control signal. the key control is intended for use with level sensitive signals such as ie, oe , cke (in registered modes only). if key control is used in situations where a short glitch on the internal match signal is unacceptable (i.e. using the key port for clk in registered modes and clk and/or cke in latched modes), it is recommended that one of the key port pins be used as a qualifier and switched after the other key port pins have stabilized to prevent glitches on the internal match signal. note that when the key control is used as an output enable, which is low active, a match will disable the i/o port driver, unless a reverse polarity is selected for output enable. pup pdn a) pull down b) normal pull up d) additional pull up low e) additional pull up high d c a b cke gc0-gcx k0-k4 c o m p a r e 5-bit tag 5 match = 1 gc0-gcx key ie clk gc0-gcx key gc0-gcx key gc0-gcx key oe gc0-gcx key x 12 12 11 device psx160 psx128b psx96b
psx family data sheet 16 revision 4.0 january 2000 1.4 i/o port assignment for nibble, byte, word and long word groups the following table shows the assignment of i/o ports for nibble, byte, word and long word groups. the psx128b and psx96b are bond out versions of the psx160. table 2 shows the i/o port pins that are made available on the psx128b and psx96b. long word number word number byte number nibble number psx160 i/o port numbers psx128b i/o port numbers psx96b i/o port numbers 0 0 0 0 p000 - p003 p000 - p003 p000 - p003 1 p004 - p007 p004 - p007 p004 - p007 1 2 p008 - p011 p008 - p011 p008 - p011 3 p012 - p015 p012 - p015 p012 - p015 1 2 4 p016 - p019 p016 - p019 p016 - p019 5 p020 - p023 p020 - p023 p020 - p023 3 6 p024 - p027 p024 - p027 p024 - p027 7 p028 - p031 p028 - p031 p028 - p031 1 2 4 8 p032 - p035 p032 - p035 p032 - p035 9 p036 - p039 p036 - p039 p036 - p039 5 10 p040 - p043 p040 - p043 p040 - p043 11 p044 - p047 p044 - p047 p044 - p047 3 6 12 p048 - p051 p048 - p051 p048 - p051 13 p052 - p055 p052 - p055 p052 - p055 7 14 p056 - p059 p056 - p059 p056 - p059 15 p060 - p063 p060 - p063 p060 - p063 2 4 8 16 p064 - p067 17 p068 - p071 9 18 p072 - p075 19 p076 - p079 not 5 10 20 p080 - p083 available 21 p084 - p087 11 22 p088 - p091 23 p092 - p095 not 3 6 12 24 p096 - p099 p096 - p099 available 25 p100 - p103 p100 - p103 13 26 p104 - p107 p104 - p107 27 p108 - p111 p108 - p111 7 14 28 p112 - p115 p112 - p115 29 p116 - p119 p116 - p119 15 30 p120 - p123 p120 - p123 31 p124 - p127 p124 - p127 table 2. i/o port assignment for nibble, byte, word and long word
psx family data sheet january 2000 revision 4.0 17 1.5 rapidconnect switching interface the rapidconnect switching interface allows the switch matrix connections to be changed quickly by providing direct write access to the switch matrix sram cells. the rapidconnect interface shown in figure 10 is a write only interface. it uses address, data and control signals to write to the switch matrix sram cells.the switch matrix sram cells are addressed as a two dimensional matrix, requiring a row address and column address to uniquely identify the sram cell(s) being written to. figure 10. psx rapidconnect system interface on the psx160, psx128b and psx96b devices, the rapidconnect interface consists of an 8-bit row address, ra[7:0], 4-bit column group address, ca[3:0], 4-bit data bus, data[3:0], write enable, we and a write strobe, strobe . the row address, column group address and data values for the different rapidconnect operations are calculated as shown in the section rapidconnect address computation. in a typical system, an embedded processor will compute the required row address, column group address and data values and apply them to the psx device. alternatively, these values could be computed before hand using the i-cube supplied software, and stored in a lookup table. upon power-up all switch matrix sram cells are cleared, all i/o ports are set to nc and the rapidconnect mode is enabled. 1.6 jtag-based configuration controller in the psx devices, the i/o attributes and switch matrix connections can be programmed using the jtag serial bus. additionally, the rapidconnect switching interface, used for dynamically changing switch matrix connections, can be enabled or disabled using the jtag serial bus. in most cases, the user does not need to know the details of the jtag protocol. the i-cube supplied software will automatically generate the necessary bit stream from a higher-level textual description of the required configuration. 1.6.1 jtag interface the jtag interface is a serial interface and uses four pins: test data in (tdi), test data out (tdo), test clock (tck), and test mode select (tms). tck is used to clock data in and out of tdi and tdo. tms, in conjunction with tdi implements a state machine that controls the various operations of the jtag protocol. in addition, the device reset signal (trst*) is used to reset both the device and the jtag controller. cpu address bus jtag config- uration control logic decode logic row address low order address 8 data strobe tck tms tdi tdo clk data bus psx we column group address high order address 4 4 4 8 16 32 p128 - p131 p128 - p131 p128 - p131 33 p132 - p135 p132 - p135 p132 - p135 17 34 p136 - p139 p136 - p139 p136 - p139 35 p140 - p143 p140 - p143 p140 - p143 9 18 36 p144 - p147 p144 - p147 p144 - p147 37 p148 - p151 p148 - p151 p148 - p151 19 38 p152 - p155 p152 - p155 p152 - p155 39 p156 - p159 p156 - p159 p156 - p159 long word number word number byte number nibble number psx160 i/o port numbers psx128b i/o port numbers psx96b i/o port numbers table 2. i/o port assignment for nibble, byte, word and long word (continued)
psx family data sheet 18 revision 4.0 january 2000 1.6.2 i/o port configuration i/o port configuration is accomplished by loading the appropriate bit stream into the programming registers present at each i/o port. only the jtag interface can be used to load these programming registers. 1.6.3 switch matrix configuration the contents of the sram cells controlling switch matrix connections can be modified using either the jtag interface or the rapidconnect interface. the jtag serial interface is used to load the data, one word at a time into the sram cells in the switch matrix. the rapidconnect mode, on the other hand, provides direct write access to sram cells in the switch matrix. when using the jtag interface to change the switch matrix configuration, the rapidconnect mode must first be disabled by resetting the rapidconnect enable flag in the mode control register (see the section miscellaneous details). 1.6.4 mode control register configuration the psx device contains a mode control register. certain bits in the register, used to store certain user flags such as rapidconnect enable and other flags which must be set correctly for the proper functioning of the device, can be changed using the jtag interface. 2.0 m iscellaneous d etails 2.1 device reset to ensure proper operation, the device reset pin, trst* must be held low during power up. the reset pulse must be at least 200ns long. the recommended reset circuitry is shown in figure 11 using an external supervisor device. it should be noted that the trst* pin must not be driven by any devices which cannot guarantee a low signal during power-up. improper devices are these whose pins are either high or tristated during power-up. examples of such devices are sram- based fpgas. the device can be reset by pulsing trst* low or by shifting in the jtag instruction reserved for device reset (this is different from the jtag reset instruction, which resets only the jtag state machine). when the device is reset, the i/o ports return to their default state of no connect (nc), the switch matrix sram cells are cleared and the rapidconnect mode is enabled. the psx device is ready for configuration as soon as it comes out of reset. the edge and level-sensitive flip-flops in the i/o port buffers are not cleared by device reset and will have unknown output values after reset. figure 11. reset circuit 2.2 mode control register the psx device contains a 16-bit mode control register. it stores the rapidconnect enable flag and certain other flags which must be set correctly for the proper functioning of the device. for more information see the psx family register programming users reference. 2.3 mixed voltage operation there are three distinct sources for power on the psx device. the first one called v dd is a 5v source and is used to power the device core, including the switch matrix sram cells, i/o port logic (excluding the i/o pin driver buffer), i/o control logic, jtag logic (except tdo pin driver) and other circuitry. the i/o buffer drivers are powered by either v dd .pad1 or v dd .pad2. table provides the details on power source assignment. v dd .pad1 and/or v dd .pad2 can be connected to either a 5v or 3v supply. this makes it easy to interface these device to 5v or 3v logic level. the tdo pin is driven by v dd .pad2. vdd ref gnd rst rst pbrst iqx supervisor +5 vmon trst*
psx family data sheet january 2000 revision 4.0 19 3.0 r apid c onnect a ddress c omputation the 160 i/o ports on the psx160 can be configured into 40 nibbles, 20 bytes, 10 words or 5 long words for switching. on the psx128b and psx96b, bondout versions of the psx160, 128 and 96 i/o ports are externally accessible. see the psx pin summary section for details. table 3 shows how to compute the rapidconnect addresses for changing connections. table 3 also shows the d ata values for unicast and multicast and clear operations. ra[7], which is not shown in the tables, indicates the configuration ban k for the write operation. (1) for psx96b, ra[4] is not available externally, but is internally forced to a0. for psx96b, all legal row address calculations should result in ra[4] = 0 or dont care (2) bin function is the n-bit binary equivalent value. (3) decode function decodes a two-bit binary value, i.e., decode(00) = 0001, decode(01) = 0010, decode(10) = 0100 & decode (11) = 1000. (4) data[3:0] is the previous value used in a make/break operation involving i and another k that is in the same 4-column grou p, i.e., integer(j/4) = integer(k/4) mode operation row address ra[6:0] column group address ca[3:0] data[3:0] for make data[3:0] for break u n i c a s t change connection between nibbles i & j [0 i < j 39] ra[6] = 0; ra[5:0] =bin(i)[5:0] 2 ca[3:0] = bin(j)[5:2] decode 3 (bin(j)[1:0]) 0000 change connection between bytes i & j [0 i < j 19] ra[6] = 1; ra[5:1] = bin(i)[4:0] ra[0] = 0 ca[3:0] = (bin(j)[4:1] if bin(j)[0] =0 then 0011 else 1100 0000 change connection between words i & j [0 i < j 9] ra[6] = 1; ra[5:2] = bin(i)[3:0] ra[1:0] = 01 ca[3:0] = bin(j)[3:0] 1111 0000 change connection between lwords i & j [0 i < j 4] ra[6:3] = 1101; ra[2:0] = bin(i)[2:0] ca[3:1] = bin(j)[2:0] ca[0] = dont care 1111 0000 m u l t i c a s t change connection between nibbles i & j [0 i < j 39] ra[6] = 0; ra[5:0] = bin(i)[5:0] ca[3:0] = bin(j)[5:2] data[3:0] 4 ored with decode(bin(j)[1:0]) data[3:0] anded with inverted decode(bin(j)[1:0]) change connection between bytes i & j [0 i < j 19] ra[6] = 1; ra[5:1] = bin(i)[4:0] ra[0] = 0 ca[3:0] = bin(j)[4:1] if bin(j)[0] = 0 then data[3:0] ored with 0011 else data[3:0] ored with 1100 if bin(j)[0] = 0 then data[3:0] anded with 1100 else data[3:0] anded with 0011 change connection between words i & j [0 i < j 9] ra[6] = 1; ra[5:2] = bin(i)[3:0] ra[1:0] = 01 ca[3:0] = bin(j)[3:0] 1111 0000 change connection between lwords i & j [0 i < j 4] ra[6:3] = 1101; ra[2:0] = bin(i)[2:0] ca[3:1] = bin(j)[2:0] ca[0] = dont care 1111 0000 c l r clear switch matrix configuration cells (break all connections) 1101111 dont care dont care dont care table 3. making/breaking a connection
psx family data sheet 20 revision 4.0 january 2000 4.0 i n s ystem c onfiguration u sing jtag- based c onfiguration c ontroller the primary configuration mode for the psx devices is the jtag-based serial mode. the jtag-based serial configuration mode allows the user to initialize the device, configure the i/o ports and establish connections through the switch matrix. in addition, the rapidconnect interface can be used for changing switch matrix connections dynamically and quickly. even if the user is planning to use rapidconnect for dynamic switching, the device must first be initialized using jtag. configuring the device using jtag involves two steps. in the first step, the user generates the bit stream, which, when loaded into the device, establishes the desired configuration. two different software options - off-line and embedded bit stream generation - are available to accomplish this task, depending on the target application. the second step is the actual downloading of the bit stream into the device. the downloading circuitry can take on different forms, depending on the target application. figure 12. off-line bit stream generation figure 13. embedded bit stream generation 4.1 bit stream generation the configuration bit stream can be generated off-line or in- system by an embedded cpu using one of the following methods: ? by using i-cube development system software products ids100 or ids200. ? by user written code based on the information provided in the psx family register programming users reference. if the bit stream is generated off-line then, depending on the application, it is either stored in non-volatile memory or directly downloaded from a host processor such as a pc connected to the target hardware. the software used for off-line generation accepts a text file describing the desired configuration - connections between different i/o ports and functional attributes of each i/o port - and generates a file containing the bit stream. this software is a part of the development system available on pc and sparcstation. 4.2 bit stream downloading the bit stream can be downloaded into the psx device using several different hardware schemes. the choice depends on the end application. all these schemes use the standard jtag protocol and timing. as per the jtag protocol, the clock signal (tck) must be supplied externally. if the target hardware is controlled by a computer such as a pc, the parallel port on the computer can be used to download the bit stream. i-cube provides a software utility to perform the downloading. under this scheme, the necessary data for tdi and tms pins as well as the (software generated) tck clock signal are sent over the parallel port. an on-board eprom or e 2 prom, in either bit-wide or byte-wide configuration, or a serial e 2 prom can be used to store the bit stream. using minimal external logic, the bit stream stored in one of these devices can be downloaded into the psx device(s) over the tdi and tms pins, with the tck pin used for synchronization. the clock signal for the tck pin is generated by the external logic. if the target system has an on-board microcontroller, the bit stream data can be read from memory (either an eprom or sram) and downloaded into the psx device(s) using 3 i/o pins on the microcontroller to generate the required tdi, tms and tck signals. the microcontroller/microprocessor, for real-time applications, can generate the bit stream and then download it into the psx device in a single operation. create configuration file (text file) compile configuration file to create configuration bitstream convert bitstream for use with configuration circuitry in the target system serial eprom eprom onboard microcontroller download cable memory configuration circuitry psx application software psx programming library
psx family data sheet january 2000 revision 4.0 21 the actual time required to download the configuration bit stream and program a psx device depends on the device(s) used, the users specific configuration pattern, and jtag clock frequency. table shows the number of jtag cycles and configuration time required for some typical operations. the size of the memory (number of bits) required is two times the number of jtag cycles.
psx family data sheet 22 revision 4.0 january 2000 5.0 c onfiguration t ime and b it s tream s ize table 4 shows the jtag cycle counts, configuration times and bit stream size for some typical operations (based on 10mhz tck). 5.1 configuring multiple psx devices the jtag-based controller allows a single device or multiple operation. for multiple device configuration, the pins are connected as shown in figure 14. figure 14. configuring multiple psx devices during the initial configuration sequence, the internal controllers on all psx devices are first brought to their reset state by pulsing the trst* reset pin low. this is followed by the actual configuration bit stream, which is downloaded into the psx devices over the tdi and tms pins. operation psx160 psx128b psx96b # of jtag cycles config. time bit- stream size # of jtag cycles config. time bit-stream size # of jtag cycles config. time bit-stream size jtag reset sequence 5 500 ns 10 bits 5 500 ns 10 bits 5 500 ns 10 bits set all i/o ports to their default value 27 2.70 m s 54 bits 27 2.70 m s 54 bits 27 2.70 m s 54 bits enable or disable rapidconnect 42 4.2 m s 84 bits 42 4.2 m s 84 bits 42 4.2 m s 84 bits change iob attributes of one i/o port 70 7.0 m s 140 bits 70 7.0 m s 140 bits 70 7.0 m s 140 bits change iob attributes of all i/o ports 160 * 70 or 11,200 1.12 ms 22,400 bits 128 * 70 or 8,960 0.896 ms 17,920 bits 96 * 70 or 6,720 0.672 ms 13,440 bits reset jtag controller + reset all i/o + clear all sram cells in both banks (this is equivalent to a hardware reset using trst*) 5 + 27 + 2 * 27 or 86 8.6 m s 172 bits 5 + 27 + 2 * 27 or 86 8.6 m s 172 bits 5 + 27 + 2 * 27 or 86 8.6 m s 172 bits connect or disconnect two nibbles, assumes second -level sram cells are set to a correct value. this operation involves writing to one first-level sram word in one bank 66 6.6 m s 132 bits 66 6.6 m s 132 bits 66 6.6 m s 132 bits connect or disconnect two bytes, words or long words, assumes the first-level sram cells are set to a correct value. this operation involves writing to one second-level sram word in one bank 66 6.6 m s 132 bits 66 6.6 m s 132 bits 66 6.6 m s 132 bits clear all sram cells (first and second-level) in one bank 27 2.70 m s 54 bits 27 2.70 m s 54 bits 27 2.70 m s 54 bits clear all sram cells (first and second-level) in both banks 2 * 27 or 54 5.4 m s 108 bits 2 * 27 or 54 5.4 m s 108 bits 2 * 27 or 54 5.4 m s 108 bits completely configure the device (all i/o and one bank) approx. 16,000 1.6 ms approx. 4 kb approx. 13,000 1.30 ms approx. 3.25 kb approx. 10,000 1.0 ms approx. 2.5 kb completely configure entire device (all i/o and both banks) approx. 20,000 2.0 ms approx. 5 kb approx. 17,000 1.70 ms approx. 4.25 kb approx. 13,000 1.30 ms approx. 3.25 kb table 4. number of jtag cycles and configuration time (using a 10 mhz jtag clock) tdi psx psx psx u3 u2 u1 tdo tck tms trst* tdi tck tms trst* tdo tdi tck tms trst* tdo tdi tck tms trst* tdo
psx family data sheet january 2000 revision 4.0 23 6.0 p in s ummary note: (1) ra4 is not available externally on the psx96b. it is connected to v ss internally psx160 psx128b psx96b (1) dir description p000 - p159 p000 - p063, p96 - p159 [p064 - p095 are not available] p000 - p063, p128 - p159 [p064 - p127 are not available] i/o i/o ports addressable as nibbles, bytes, words and long words gc0 - gc12 gc0 - gc12 gc0 - gc11 i general purpose control pins used for clock, clock enable, input enable and output enable signals k0 - k4 k0 - k4 k0 - k4 i key control pins additional control pins used to generate clk, cke, ie and oe signals. refer to section i/o control signals. ra0 - ra7 ca0 - ca3 data0 - data3 we strobe ra0 - ra7 ca0 - ca3 data0 - data3 we strobe ra0 - ra3, ra5 - ra7 ca0 - ca3 data0 - data3 we strobe i i i i i rapidconnect control pins row address vector column group address vector data bus rapidconnect write enable rapidconnect write strobe bank bank bank i active bank select trst* trst* trst* i hardware reset refer to section on device reset tdi, tms, tck, tdo tdi, tms, tck, tdo tdi, tms, tck, tdo i o jtag pins for downloading the serial configuration bitstream v dd .pad1 v dd .pad2 v dd v ss v dd .pad1 v dd .pad2 v dd v ss v dd .pad1 v dd .pad2 v dd v ss p p p p power & ground pins power pins for group 1 i/o buffer drivers power pins for group 2 i/o buffer drivers power pins for on-chip circuitry and pins other than i/o buffer drivers ground pins table 5. psx pin summary supply voltage pins powered by supply voltage v dd ra[0:7], ca[0:3],data[0:3], gc[0:12], key[0:4], we, strobe, bank, tdi, tms, tck, trst*, v dd .pad1 p000:p015, p024:p039, p056:p071, p088:p103, p120:p135 v dd .pad2 p016:p023, p040:p055, p072:p087, p104:p119, p136:p159, tdo table 6. supply voltage source
psx family data sheet 24 revision 4.0 january 2000 7.0 e lectrical s pecifications unless otherwise stated, the specifications apply to all psx devices. 7.1 absolute maximum rating (1) 7.2 recommended operating conditions (2) 7.3 capacitance (3) notes: (1) exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) a maximum overshoot and undershoot of 2v for a maximum duration of 20 ns is acceptable. (3) capacitance measured at 25c. sample-tested only. symbol parameter limits units v dd supply voltage to ground -0.3 to +7.0 v v dd .pad1,2 supply voltage for i/o buffer driver -0.3 to +7.0 v v in (2) input voltage -0.3 to (v dd .pad + 0.3) v t j junction temperature 150 c t stg storage temperature -65 to +150 c i sink sink current per port pin - 150 ma table 7. absolute maximum ratings symbol parameter limits units v dd supply voltage to ground 4.75 to 5.25 v v dd .pad1,2 supply voltage for i/o buffer driver (v dd .pad1 and v dd .pad2 can operate at different voltages) 4.75 to 5.25 or 2.96 to 3.63 v v t a operating temperature 0 to +70 c table 8. recommended operating conditions symbol parameter psx160 psx128b psx96b units min max min max min max c in input capacitance (jtag pins) - 8 - 8 - 8 pf c out output capacitance (tdo pin) - 8 - 8 - 8 pf c port i/o signal port capacitance - 10 - 10 - 10 pf c cntl general control, key control and rapidconnect pin capacitance -8- 8-8 pf table 9. capacitance
psx family data sheet january 2000 revision 4.0 25 7.4 dc electrical specifications (t a = 0 c to 70 c, v dd = 5v 5%; v dd .pad1,2 = 5v5%, or v dd .pad1,2 = 3.3v10%). notes: (1) these parameters are guaranteed but not tested in production. (2) no more than one output should be tested at a time and the duration of the test should be less than one second. symbol parameter conditions psx160, psx128b, psx96b units min max v ih high-level input voltage 2.0 v dd + 0.3 v v il low-level input voltage -0.3 0.8 v v oh high-level output voltage v dd = min, v dd .pad = 4.75v i oh = - 8 ma 2.4 - v high-level output voltage v dd = min, v dd .pad = 2.97v i oh = - 4ma 2.4 - v v ol low-level output voltage v dd = min, v dd .pad = 4.75v i ol = 16 ma - 0.4 v low-level output voltage v dd = min, v dd .pad = 2.97v i ol = 16 ma - 0.4 v |i ih |, |i il | input leakage current for i/o ports v dd = max, 0 v in v dd .pad - 5 m a i pt i/o port trickling current (1) v dd = max, 0 v in v dd .pad - -25 m a |i oz | tristate output off-state current v dd = max, 0 v in v dd .pad - 5 m a i pu-wk programmed-weak additional pull-up current v dd = min, v dd .pad = 4.75v v o = gnd 2.5 4.5 ma i pu-sg programmed-strong additional pull-up current v dd = min, v dd .pad = 4.75v v o = gnd 12 20 ma i os short circuit current (1, 2) v dd = max, v dd .pad = 5.25v v o = gnd -60 - ma i ddq_core quiescent core power supply current v dd = max, v dd .pad = 5.25v all i/os = nc, v o = gnd - 3.0 ma i ddq_pad quiescent pad power supply current v dd = max, v dd .pad = 5.25v all i/os = nc, v o = gnd -80a q ddd total dynamic power supply current per input/output pair (1) v dd = max, v dd .pad = 5.25v, no load, @ 1.0 mhz clock input, connect one output per input - 0.15 ma/ mhz table 10. dc electrical specification
psx family data sheet 26 revision 4.0 january 2000 7.5 ac electrical specifications (ta = 0c to 70c, vdd = 5v5%; vdd.pad1,2 = 5v5%, or vdd.pad1,2 = 3.3v10%. assume two i/o ports connected through the switch matrix with 35 pf external loading.) speed grade -133 -100 units reference figure symbol parameter min max min max f rio register input/output, clock frequency (1) 133 100 mhz t w-rio register input/output, clock pulse width, low or high 3.5 4.5 ns t s-rio register input/output, data setup time to clk 3.0 3.0 ns figure 16 t h-rio register input/output, clk to data hold time 2.5 2.5 ns t co-rio register input/output, clock to output data valid 7.5 10.0 ns f ri register input, clock frequency (1) 133 100 mhz t w-ri register input, clock pulse width, low or high 3.5 4.5 ns t s-ri register input, data setup time to clk 3.0 3.0 ns figure 17 t h-ri register input, clk to data hold time 3.0 3.0 ns t co-ri register input, clock to output data valid 11.0 13.5 ns f ro register output, clock pulse frequency (1) 133 100 mhz figure 18 t w-ro register output, clock width, low or high 3.5 4.5 ns t s-ro register output, data setup time to clk 5.0 6.0 ns t h-ro register output, clk to data hold time 0.0 0.0 ns t co-ro register output, clock to output data valid 7.5 10.0 ns t phl t plh one way signal propagation delay 7.0 9.0 ns t d br additional delay in bus repeater (br) mode 0.0 0.0 ns t sk skew between output ports (1) 1.5 1.5 ns t w+ input flow through positive pulse width 5.5 6.5 ns t w- input flow through negative pulse width 5.5 6.5 ns r data nrz data rate (1) 160 133 mb/s t pzh-ot , t pzl-ot output enable (gc) to data valid 9.5 11.5 ns figure 20 t phz-ot , t plz-ot output enable (gc) to output at high z (1) 9.5 11.5 ns t pzh-it , t pzl-it input enable (gc) to data valid 9.5 11.5 ns figure 21 t phz-it , t plz-it input enable (gc) to output at high z (1) 9.5 11.5 ns t w-li latch input, latch enable (gc) pulse width, low or high 3.3 4.5 ns t s-li latch input, data setup time to latch enable (gc) trailing edge 3.0 3.0 ns t h-li latch input, data to latch enable (gc) trailing edge hold time 1.0 1.0 ns figure 22 t co-li latch input, latch enable (gc) leading edge to data out delay 11.0 13.5 ns t p-lit latch input, transparent mode propagation delay 9.0 11.0 ns t w-lo latch output, latch enable (gc) pulse width, low or high 3.3 4.5 ns t s-lo latch output, data setup time to latch enable (gc) trailing edge 5.0 6.0 ns t h-lo latch output, data to latch enable (gc) trailing edge hold time 0.0 0.0 ns figure 23 t co-lo latch output, latch enable (gc) leading edge to data out delay 7.5 10.0 ns t p-lot latch output, transparent mode propagation delay 9.0 11.0 ns table 11. ac electrical specifications
psx family data sheet january 2000 revision 4.0 27 note: (1) these parameters are guaranteed but not tested in production. t kw-ri register input, minimum pulse width of key as clock enable, low or high (1) 5.0 6.0 ns figure 24 t ks-ri register input, clock enable (key) setup time to clk (gc) (1) 3.0 3.0 ns t kh-ri register input, clk (gc) to clock enable (key) hold time (1) 1.0 1.0 ns t kco-ri register input, key clock to output data valid (1) 11.0 13.5 ns t kw-ro register output, minimum pulse width of key as clock enable, low or high (1) 5.0 6.0 ns t ks-ro register output, clock enable (key) setup time to clk (gc) (1) 3.0 3.0 ns figure 25 t kh-ro register output, clk (gc) to clock enable (key) hold time 1.0 1.0 ns t kco-ro register output, key clock to output data valid 7.5 10.0 ns t kpzh-ot t kpzl- ot output enable (key) to data valid (1) 9.5 11.5 ns figure 26 t kphz-ot t kplz- ot output enable (key) to output at high z (1) 9.5 11.5 ns t kpzh-it t kpzl-it input enable (key) to data valid (1) 9.5 11.5 ns figure 27 t kphz-it t kplz-it input enable (key) to output at high z (1) 9.5 11.5 ns t kw-li latch input, minimum pulse width of key as latch enable, low or high (1) 5.0 6.0 ns t ks-li latch input, data setup time to latch enable (key) trailing edge (1) 3.0 3.0 ns t kh-li latch input, data to latch enable (key) trailing edge hold time (1) 1.0 1.0 ns figure 28 t kco-li latch input, latch enable (key) leading edge to data out (1) 11.0 13.5 ns t kp-lit latch input, transparent mode propagation delay (1) 9.0 11.0 ns t kw-lo latch output, minimum pulse width of key as latch enable, low or high 5.0 6.0 ns t ks-lo latch output, data setup time to latch enable (key) trailing edge 5.0 6.0 ns t kh-lo latch output, data to latch enable (key) trailing edge hold time 0.0 0.0 ns figure 29 t kco-lo latch output, latch enable (key) leading edge to data out 11.0 12.5 ns t kp-lot latch output, transparent mode propagation delay 9.0 11.0 ns t rc rapidconnect strobe period 12.0 13.5 ns t w+ -rc t w- -rc rapidconnect strobe pulse width 5.0 4.5 6.0 5.5 ns t s-rc rapidconnect address and data setup time 4.0 4.0 ns figure 30 t h-rc rapidconnect address and data hold time 0.0 0.0 ns t p-rc rapidconnect strobe falling edge to data valid for making connection 13.0 15.0 ns f jtag jtag clock (tck) frequency 10 10 mhz t w-jtag jtag clock (tck) pulse width 20.0 20.0 ns t s-jtag jtag setup time 4.0 4.5 ns figure 31 t h-jtag jtag hold time 0.0 0.5 ns t p-jtag jtag clock to output data valid 15.0 15.0 ns t bo bank to output data valid 9.5 11.5 ns speed grade -133 -100 units reference figure symbol parameter min max min max table 11. ac electrical specifications (continued)
psx family data sheet 28 revision 4.0 january 2000 7.6 parameter de-rating for one-to-many connections symbol parameter -133 -100 units min max min max cn max maximum number of connections per input - 19 - 19 d t pd increase in t pd for every additional output port connected to an input port - 0.45 - 0.50 ns d t w increase in tw+ and tw- for every additional output port connected to an input port - 0.50 - 0.55 ns d f decrease in maximum operating frequency every additional output port connected to an input port - 1.5 - 2.0 mhz table 12. parameter de-rating for one-to-many connections
psx family data sheet january 2000 revision 4.0 29 7.7 test circuit and timing diagrams figure 15. test circuit and waveform definition figure 16. registered input and registered output mode timing (iclk/oclk synchronized) figure 17. registered input mode timing 50 w v dd .pad 500 w 35pf* pulse generator d.u.t. vin vout 500 w 7.0v * load capacitance includes jig and probe capacitance. t plz /t pzl closed all others open parameter tested switch position 3.0v 1.5v 0v t r t f t r t f t w 90% 10% negative pulse 3.0v 1.5v 0v 90% 10% positive pulse t f = 3 ns (max) t r = 3 ns (max) d n d n+1 t co-rio d n-2 d n d n-1 outport t w-rio t w-rio t s-rio t h-rio gc (clk) inport d ce q out port d ce q clk inport switch matrix ri ro t co-ri outport t w-ri t w-ri t s-ri t h-ri gc (clk) inport d n-1 d n d n+1 d n d n+1 ri op inport outport switch matrix d ce q clk
psx family data sheet 30 revision 4.0 january 2000 figure 18. registered output mode timing figure 19. i/o port timing (flow-through mode) figure 20. output enable timing (flow-through mode) t co-ro d n-1 d n d n+1 d n d n+1 outport t w-ro t w-ro t s-ro t h-ro gc (clk) inport inport out port ro in swtich matrix d ce q clk 1.5v inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 gc (oe) outport t pzh-ot t pzl-ot t plz-ot t phz-ot v ol + 0.3v v oh - 0.3v v ol v oh inport oe in op outport inport switch matrix
psx family data sheet january 2000 revision 4.0 31 figure 21. input enable timing (flow-through mode) figure 22. latched input mode timing figure 23. latched output mode timing gc (ie) outport t pzh-it t pzl-it t plz-it t phz-it inport in op outport inport switch matrix ie switch matrix op inport outport t co-li t p-lit t s-li t h-li t w-li gc (clk) inport outport li d le q clk switch matrix lo inport outport in t co-lo t p-lot t s-lo t h-lo t w-lo gc (clk) inport outport d le q clk
psx family data sheet 32 revision 4.0 january 2000 figure 24. key timing for register input, clock enable (cke) figure 25. key timing for register output, clock enable (cke) figure 26. key timing for output enable inport outport ri op switch matrix t ks-ri t kh-ri gc (clk) key (cke ) inport outport valid t kw-ri t kco-ri d ce q clk cke inport outport ro in switch matrix t ks-ro t kh-ro gc (clk) key (cke) inport outport valid t kw-ro t kco-ro d ce q clk cke key (oe) outport t kpzh-ot t kpzl-ot t kplz-ot t kphz-ot v ol + 0.3v v oh - 0.3v v ol v oh inport oe in op outport inport valid valid switch matrix
psx family data sheet january 2000 revision 4.0 33 figure 27. key timing for input enable figure 28. key timing for latch input, enable (cke) figure 29. key timing for latch output, enable (cke) outport t kpzh-it t kpzl-it t kplz-it t kphz-it inport in op outport inport switch matrix ie key (ie) valid valid inport outport li op switch matrix t kco-li t ks-li t kh-li gc (clk) key (cke) inport outport valid t kp-lit d le q clk cke t kco-lo t ks-lo t kh-lo gc (clk) key (cke) inport outport valid t kp-lot switch matrix in lo inport d le q clk cke outport
psx family data sheet 34 revision 4.0 january 2000 figure 30. rapidconnect timing figure 31. jtag timing t rc t s-rc t p-rc t s-rc t s-rc t h-rc t h-rc t s-rc t w-rc t w-rc strobe output port we make connection break connection ra[7:0] ca[3:0] data[3:0] t p-jtag t s-jtag t h-jtag t w-jtag t w-jtag tck tdi, tms tdo
psx family data sheet january 2000 revision 4.0 35 7.8 external ac timing characteristics as functions of internal ac timing characteristics the following table shows the relationship between external and internal timing parameters described in the next section. symbol equation t plh , t phl tp_ipad + tp_itsb + tp_sw + tp_a_o + tp_otsb t p d d tp_sw t pzl-ot , t pzh-ot tp_gc + tz_otsb t plz-ot , t phz-ot tp_gc + tz_otsb t pzl-it , t pzh-it tp_gc + tz_itsb t plz-it , t phz-it tp_gc + tz_itsb t s-ri tp_ipad + ts_r - tp_gc t h-ri tp_gc + th_r - tp_ipad t co-ri tp_gc + tco_ri + tp_sw + tp_a_o + tp_otsb t s-ro (tp_ipad + tp_itsb + tp_sw + tp_a_o) + ts_r - tp_gc t h-ro tp_gc + th_r - (tp_ipad + tp_itsb + tp_sw + tp_a_o) t co-ro tp_gc + tco_ro t s-rio tp_ipad + ts_r - tp_gc t h-rio tp_gc + th_r - tp_ipad t co-rio tp_gc + tco_ro t s-li tp_ipad + ts_l - tp_gc t h-li tp_gc + th_l - tp_ipad t co_li tp_gc + tco_li + tp_sw + tp_a_o + tp_otsb t p-lit tp_ipad + tco_li + tp_sw + tp_a_o + tp_otsb t s-lo (tp_ipad + tp_itsb + tp_sw + tp_a_o) + ts_l - tp_gc t h-lo tp_gc + th_l - (tp_ipad + tp_itsb + tp_sw + tp_a_o) t co-lo tp_gc + tco_lo t p-lot tp_ipad + tp_itsb + tp_sw + tp_a_o + tco_lo t kpzl-ot , t kpzh-ot tp_ky + tz_otsb t kplz-ot , t kphz-ot tp_ky + tz_otsb t kpzl-it , t kpzh-it tp_ky + tz_itsb t kplz-it , t kphz-it tp_ky + tz_itsb t ks-ri tp_ipad + ts_r - tp_ky t kh-ri tp_ky + th_r - tp_ipad t kco-ri tp_ky + tco_ri + tp_sw + tp_a_o + tp_otsb t ks-ro (tp_ipad + tp_itsb + tp_sw + tp_a_o) + ts_r - tp_ky t kh-ro tp_ky + th_r - (tp_ipad + tp_itsb + tp_sw + tp_a_o) t kco-ro tp_ky + tco_or t ks-li tp_ipad + ts_l - tp_ky t kh-li tp_ky + th_l - tp_ipad t kco-li tp_ky + tco_li + tp_sw + tp_a_o + tp_otsb t ks-lo (tp_ipad + tp_itsb + tp_sw + tp_a_o) + ts_l - tp_ky t kh-lo tp_ky + th_l - (tp_ipad + tp_itsb + tp_sw + tp_a_o) t kco-lo tp_ky + tco_lo table 13. external ac timing characteristics
psx family data sheet 36 revision 4.0 january 2000 7.9 internal ac timing characteristics for -133 speed grade (all times are in ns) internal timing parameters and corresponding circuit models are described below. the timing values are based on simulation data for a psx160-133. the reference numbers correspond to those in the internal timing models on the following pages. symbol parameter 5.25v 0 c 4.75v 70 c reference number tp_itsb input buffer delay. the propagation delay for data path through input buffer (excluding the pad buffer delay). 0.7 1.6 tz_itsb input enable delay. the delay from assertion of the enable node to the time the array line is driven to an active level. 0.7 1.6 input tristate delay. the delay from de-assertion of the enable node to the time the array line floats to a high-z state. tp_ipad input pad buffer delay. 0.45 1.0 tp_gc control line delay. the delay from assertion of input control pin to internal node (includes pad and mux delays). 1.8 4.0 tp_ky key bus delay. the delay from a valid key value to internal node (includes pad, comparator and mux delays). 3.4 6.5 tp_otsb output buffer delay. the propagation delay for data path through input buffer (includes pad delay). 0.9 2.0 tz_otsb output enable delay. the delay from assertion of the enable node to the time the output pin is driven to an active level. 0.8 2.0 output tristate delay. the delay from de-assertion of the enable signal to the time the output pin floats to a high-z state. tp_a_o array to out delay. the propagation delay from output of switch matrix to entrance node of output stage. 0.45 1.0 tp_li input latch delay. the propagation delay through a transparent input latch. 0.9 1.9 tp_lo output latch delay. the propagation delay through a transparent output latch. 1.0 2.0 ts_l latch setup time. the time required for a signal to be stable at the latch input before the active level of clock or clock enable. 0.5 1.0 th_l latch hold time. the time required for a signal to be stable at the latch input after the active level of clock or clock enable. 0.0 0.0 tco_li input latch clock to out. the time required to obtain a held output (array line) after the active level of clock or clock enable. also, the time required to obtain a tracking output after the inactive level of clock or clock enable (excludes control line delay). 0.4 0.8 tco_lo output latch clock to out. the time required to obtain a held pin output after the active level of clock or clock enable. also, the time required to obtain a tracking pin output after the inactive level of clock or clock enable (excludes control line delay). 0.4 0.8 ts_r register setup time. the time required for a signal to be stable at the register input before the active edge of clock or active level of clock enable 0.5 1.0 th_r register hold time. the time required for a signal to be stable at the register input after the active edge of clock or active level of clock enable. 0.0 0.0 tco_ri input register clock to out. the time required to obtain a valid output (array line) after the active edge of clock or active level of clock enable (excludes control line delay). 0.5 1.0 tco_ro output register clock to out. the time required to obtain a valid pin output after the active edge of clock or active level of clock enable (excludes control line delay). 0.5 1.0 tp_bsel propagation delay from bank select pin to output of preconnected output buffer 2.1 3.5 tp_sw propagation delay through switch matrix (one load) 0.45 1.0 table 14. internal ac timing characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
psx family data sheet january 2000 revision 4.0 37 7.10 circuit models for internal timing timing models are simplified block diagrams that illustrate internal propagation delays for signal paths and control paths. figure 32. internal timing model 1: flow through (from input to switch matrix) figure 33. internal timing model 2: flow through (from switch matrix to output) figure 34. internal timing model 3: latched input (from input to switch matrix) figure 35. internal timing model 4: latched output (from switch matrix to output) 4 3 1 2 5 or 4 8 6 7 5 or 4 5 or 4 5 or 4 3 1 12 11 2 5 or eck lat eck lat 4 5 or 4 5 or 4 8 6 14 13 7 5 or
psx family data sheet 38 revision 4.0 january 2000 figure 36. internal timing model 5: registered input (from input to switch matrix) figure 37. internal timing model 6: registered output (from switch matrix to output) figure 38. internal timing model 7: switch matrix delay when switching banks figure 39. internal timing model 8: switch matrix delay reg e 4 5 or 4 5 or 4 3 1 17 2 5 or reg e 4 or 4 or 4 or 18 5 5 5 8 7 6 in out sram cell control tpd_bsel 20
psx family data sheet january 2000 revision 4.0 39 7.11 typical ac and dc characteristics 12345 12345 01020304050 70 60 0.8 1.0 1.2 1.1 0.9 ambient temperature (?) normalized delay time vs. ambient temperature normalized t phl & t plh 456 5.5 4.5 0.6 1.0 1.4 1.2 0.8 supply voltage (v) normalized delay time vs. supply voltage normalized t phl & t plh 456 4.5 5.5 0.6 0.8 1 1.4 1.2 supply voltage (v) normalized supply current vs. supply voltage (80 in x 80 out configuration for psx160) normalized i dd 50 100 150 200 250 300 -2 0 2 4 6 8 capacitance (pf) typical delay time vs. output loading delta t phl & t plh (ns) 0 v dd = 5v t a = 25? 0 20 40 60 80 100 v dd = 5v t a = 25? output voltage (v) output source current vs. output voltage output source current (ma) 0 12345 0.2 0.4 0.6 0.8 1.0 supply voltage (v) typical power-on current vs. supply voltage normalized i dd capacitance (pf) typical delay time vs. output loading delta t phl & t plh (ns) 0 200 400 600 800 1000 -2 0 4 2 8 6 12 10 16 14 t plh t phl v dd = 5v t a = 25? output voltage (v) output sink current vs. output voltage output sink current (ma) 0 20 40 60 80 100 120 v dd = 5v t a = 25? pull up current i pu-wk pull up current i pu-sg v dd = 5v t a = 25? v dd = 5v t a = 25? t plh t phl t a = 25? t plh t phl t a = 25? t a = 25? v dd = 5v t plh t phl 0 0.5 1 1.5 2 2.5 3.5 3 output voltage (v) pull up current (ma) 18 16 14 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3.5 3 output voltage (v) pull up current (ma) 4 3.5 3 2.5 2 1.5 1 0.5 0
psx family data sheet 40 revision 4.0 january 2000 8.0 p inout 8.1 psx160 [pqfp 240l package] pinout by pin location pin # name pin # name pin # name pin # name pin # name pin # name 1 gc3 41 p121 81 p081 121 ca2 161 p072 201 p097 2 gc2 42 p122 82 p082 122 ca1 162 v ss 202 p096 3 gc1 43 p123 83 p083 123 ca0 163 v dd .pad2 203 v ss 4 gc0 44 p124 84 p084 124 v dd .pad2 164 p047 204 p071 5 k4 45 p125 85 p085 125 ra7 165 p046 205 p070 6 k3 46 p126 86 p086 126 ra6 166 p045 206 p069 7 k2 47 p127 87 p087 127 ra5 167 p044 207 p068 8k148v ss 88 v ss 128 v ss 168 p043 208 p067 9 k0 49 p152 89 p112 129 ra4 169 p042 209 p066 10 v ss 50 v ss 90 p113 130 ra3 170 p041 210 p065 11 p024 51 p153 91 p114 131 ra2 171 p040 211 p064 12 p025 52 p154 92 v dd .pad2 132 ra1 172 v ss 212 v dd .pad1 13 p026 53 p155 93 p115 133 ra0 173 p015 213 v ss 14 p027 54 p156 94 p116 134 v ss 174 p014 214 p039 15 p028 55 v dd 95 p117 135 p143 175 p013 215 p038 16 p029 56 p157 96 p118 136 p142 176 p012 216 p037 17 p030 57 p158 97 p119 137 p141 177 p011 217 p036 18 p031 58 p159 98 v ss 138 p140 178 p010 218 p035 19 v dd .pad1 59 v dd .pad2 99 p144 139 p139 179 v dd .pad1 219 p034 20 v ss 60 v ss 100 p145 140 p138 180 p009 220 p033 21 p056 61 p016 101 p146 141 p137 181 p008 221 p032 22 p057 62 p017 102 p147 142 p136 182 v ss 222 v ss 23 p058 63 p018 103 p148 143 v ss 183 v ss 223 p007 24 p059 64 p019 104 p149 144 p111 184 p135 224 p006 25 p060 65 p020 105 p150 145 v dd .pad2 185 p134 225 p005 26 p061 66 p021 106 p151 146 p110 186 p133 226 p004 27 p062 67 p022 107 tdo 147 p109 187 p132 227 p003 28 p063 68 p023 108 tck 148 p108 188 p131 228 v dd .pad1 29 v ss 69 v ss 109 tdi 149 p107 189 p130 229 p002 30 p088 70 p048 110 tms 150 p106 190 p129 230 p001 31 p089 71 p049 111 trst* 151 p105 191 p128 231 p000 32 p090 72 p050 112 bank 152 p104 192 v dd .pad1 232 gc12 33 p091 73 p051 113 strobe 153 v ss 193 v ss 233 gc11 34 p092 74 v dd .pad2 114 we 154 p079 194 p103 234 gc10 35 p093 75 p052 115 data3 155 p078 195 p102 235 gc9 36 v dd .pad1 76 p053 116 data2 156 p077 196 p101 236 gc8 37 p094 77 p054 117 data1 157 p076 197 v dd 237 gc7 38 p095 78 p055 118 data0 158 p075 198 p100 238 gc6 39 v ss 79 v ss 119 v ss 159 p074 199 p099 239 gc5 40 p120 80 p080 120 ca3 160 p073 200 p098 240 gc4 table 15. psx160 [pqfp 240l package] pinout by pin location
psx family data sheet january 2000 revision 4.0 41 8.2 psx160 [pqfp 240l package] pinout by pin name name pin # name pin # name pin # name pin # name pin # name pin # bank 112 p013 175 p053 76 p093 35 p133 186 trst* 111 ca0 123 p014 174 p054 77 p094 37 p134 185 v dd 55 ca1 122 p015 173 p055 78 p095 38 p135 184 v dd 197 ca2 121 p016 61 p056 21 p096 202 p136 142 v dd .pad1 19 ca3 120 p017 62 p057 22 p097 201 p137 141 v dd .pad1 36 data0 118 p018 63 p058 23 p098 200 p138 140 v dd .pad1 179 data1 117 p019 64 p059 24 p099 199 p139 139 v dd .pad1 192 data2 116 p020 65 p060 25 p100 198 p140 138 v dd .pad1 212 data3 115 p021 66 p061 26 p101 196 p141 137 v dd .pad1 228 gc0 4 p022 67 p062 27 p102 195 p142 136 v dd .pad2 59 gc1 3 p023 68 p063 28 p103 194 p143 135 v dd .pad2 74 gc2 2 p024 11 p064 211 p104 152 p144 99 v dd .pad2 92 gc3 1 p025 12 p065 210 p105 151 p145 100 v dd .pad2 124 gc4 240 p026 13 p066 209 p106 150 p146 101 v dd .pad2 145 gc5 239 p027 14 p067 208 p107 149 p147 102 v dd .pad2 163 gc6 238 p028 15 p068 207 p108 148 p148 103 v ss 50 gc7 237 p029 16 p069 206 p109 147 p149 104 v ss 128 gc8 236 p030 17 p070 205 p110 146 p150 105 v ss 183 gc9 235 p031 18 p071 204 p111 144 p151 106 v ss 10 gc10 234 p032 221 p072 161 p112 89 p152 49 v ss 20 gc11 233 p033 220 p073 160 p113 90 p153 51 v ss 29 gc12 232 p034 219 p074 159 p114 91 p154 52 v ss 39 k0 9 p035 218 p075 158 p115 93 p155 53 v ss 48 k1 8 p036 217 p076 157 p116 94 p156 54 v ss 60 k2 7 p037 216 p077 156 p117 95 p157 56 v ss 69 k3 6 p038 215 p078 155 p118 96 p158 57 v ss 79 k4 5 p039 214 p079 154 p119 97 p159 58 v ss 88 p000 231 p040 171 p080 80 p120 40 ra0 133 v ss 98 p001 230 p041 170 p081 81 p121 41 ra1 132 v ss 119 p002 229 p042 169 p082 82 p122 42 ra2 131 v ss 134 p003 227 p043 168 p083 83 p123 43 ra3 130 v ss 143 p004 226 p044 167 p084 84 p124 44 ra4 129 v ss 153 p005 225 p045 166 p085 85 p125 45 ra5 127 v ss 162 p006 224 p046 165 p086 86 p126 46 ra6 126 v ss 172 p007 223 p047 164 p087 87 p127 47 ra7 125 v ss 182 p008 181 p048 70 p088 30 p128 191 strobe 113 v ss 193 p009 180 p049 71 p089 31 p129 190 tck 108 v ss 203 p010 178 p050 72 p090 32 p130 189 tdi 109 v ss 213 p011 177 p051 73 p091 33 p131 188 tdo 107 v ss 222 p012 176 p052 75 p092 34 p132 187 tms 110 we 114 table 16. psx160 [pqfp 240l package] pinout by pin name
psx family data sheet 42 revision 4.0 january 2000 8.3 psx160 [pqfp 240l package] pinout figure 40. psx160 [pqfp 240l package] pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 gc4 gc5 gc6 gc7 gc8 gc9 gc10 gc11 gc12 p000 p001 p002 v dd .pad1 p003 p004 p005 p006 p007 v ss p032 p033 p034 p035 p036 p037 p038 p039 v ss v dd .pad1 p064 p065 p066 p067 p068 p069 p070 p071 v ss p096 p097 p098 p099 p100 v dd p101 p102 p103 v ss v dd .pad1 p128 p129 p130 p131 p132 p133 p134 p135 v ss v ss p008 p009 v dd .pad1 p010 p011 p012 p013 p014 p015 v ss p040 p041 p042 p043 p044 p045 p046 p047 v dd .pad2 v ss p072 p073 p074 p075 p076 p077 p078 p079 v ss p104 p105 p106 p107 p108 p109 p110 v dd .pad2 p111 v ss p136 p137 p138 p139 p140 p141 p142 p143 v ss ra0 ra1 ra2 ra3 ra4 v ss ra5 ra6 ra7 v dd .pad2 ca0 ca1 ca2 top view i/o ports powered by v dd .pad2 i/o ports powered by v dd .pad1 gc3 gc2 gc1 gc0 k4 k3 k2 k1 k0 v ss p024 p025 p026 p027 p028 p029 p030 p031 v dd .pad1 v ss p056 p057 p058 p059 p060 p061 p062 p063 v ss p088 p089 p090 p091 p092 p093 v dd .pad1 p094 p095 v ss p120 p121 p122 p123 p124 p125 p126 p127 v ss p152 v ss p153 p154 p155 p156 v dd p157 p158 p159 v dd .pad2 v ss p016 p017 p018 p019 p020 p021 p022 p023 v ss p048 p049 p050 p051 v dd .pad2 p052 p053 p054 p055 v ss p080 p081 p082 p083 p084 p085 p086 p087 v ss p112 p113 p114 v dd .pad2 p115 p116 p117 p118 p119 v ss p144 p145 p146 p147 p148 p149 p150 p151 tdo tck tdi tms trst* bank strobe we data3 data2 data1 data0 v ss ca3
psx family data sheet january 2000 revision 4.0 43 8.4 psx128b [pqfp 208l package] pinout by pin location pin # name pin # name pin # name pin # name 1 gc3 53 p016 105 ca2 157 p008 2 gc2 54 p017 106 ca1 158 v ss 3 gc1 55 p018 107 ca0 159 v ss 4 gc0 56 p019 108 v dd .pad2 160 p135 5 k4 57 p020 109 ra7 161 p134 6 k3 58 p021 110 ra6 162 p133 7 k2 59 p022 111 ra5 163 p132 8 k1 60 p023 112 v ss 164 p131 9k061v ss 113 ra4 165 p130 10 v ss 62 p048 114 ra3 166 p129 11 p024 63 p049 115 ra2 167 p128 12 p025 64 p050 116 ra1 168 v dd .pad1 13 p026 65 p051 117 ra0 169 v ss 14 p027 66 v dd .pad2 118 v ss 170 p103 15 p028 67 p052 119 p143 171 p102 16 p029 68 p053 120 p142 172 p101 17 p030 69 p054 121 p141 173 v dd 18 p031 70 p055 122 p140 174 p100 19 v dd .pad1 71 v ss 123 p139 175 p099 20 v ss 72 v ss 124 p138 176 p098 21 p056 73 p112 125 p137 177 p097 22 p057 74 p113 126 p136 178 p096 23 p058 75 p114 127 v ss 179 v ss 24 p059 76 v dd .pad2 128 p111 180 v dd .pad1 25 p060 77 p115 129 v dd .pad2 181 v ss 26 p061 78 p116 130 p110 182 p039 27 p062 79 p117 131 p109 183 p038 28 p063 80 p118 132 p108 184 p037 29 v ss 81 p119 133 p107 185 p036 30 v dd .pad1 82 v ss 134 p106 186 p035 31 v ss 83 p144 135 p105 187 p034 32 p120 84 p145 136 p104 188 p033 33 p121 85 p146 137 v ss 189 p032 34 p122 86 p147 138 v ss 190 v ss 35 p123 87 p148 139 v dd .pad2 191 p007 36 p124 88 p149 140 p047 192 p006 37 p125 89 p150 141 p046 193 p005 38 p126 90 p151 142 p045 194 p004 39 p127 91 tdo 143 p044 195 p003 40 v ss 92 tck 144 p043 196 v dd .pad1 41 p152 93 tdi 145 p042 197 p002 42 v ss 94 tms 146 p041 198 p001 43 p153 95 trst* 147 p040 199 p000 44 p154 96 bank 148 v ss 200 gc12 45 p155 97 strobe 149 p015 201 gc11 46 p156 98 we 150 p014 202 gc10 47 v dd 99 data3 151 p013 203 gc9 48 p157 100 data2 152 p012 204 gc8 49 p158 101 data1 153 p011 205 gc7 50 p159 102 data0 154 p011 206 gc6 51 v dd .pad2 103 v ss 155 v dd .pad1 207 gc5 52 v ss 104 ca3 156 p009 208 gc4 table 17. psx128b [pqfp 208l package] pinout by pin location
psx family data sheet 44 revision 4.0 january 2000 8.5 psx128b [pqfp 208l package] pinout by pin name name pin # name pin # name pin # name pin # bank 96 p025 12 p109 131 ra1 116 ca0 107 p026 13 p110 130 ra2 115 ca1 106 p027 14 p111 128 ra3 114 ca2 105 p028 15 p112 73 ra4 113 ca3 104 p029 16 p113 74 ra5 111 data0 102 p030 17 p114 75 ra6 110 data1 101 p031 18 p115 77 ra7 109 data2 100 p032 189 p116 78 strobe 97 data3 99 p033 188 p117 79 tck 92 gc0 4 p034 187 p118 80 tdi 93 gc1 3 p035 186 p119 81 tdo 91 gc2 2 p036 185 p120 32 tms 94 gc3 1 p037 184 p121 33 trst* 95 gc4 208 p038 183 p122 34 v dd 47 gc5 207 p039 182 p123 35 v dd 173 gc6 206 p040 147 p124 36 v dd .pad1 19 gc7 205 p041 146 p125 37 v dd .pad1 30 gc8 204 p042 145 p126 38 v dd .pad1 155 gc9 203 p043 144 p127 39 v dd .pad1 168 gc10 202 p044 143 p128 167 v dd .pad1 180 gc11 201 p045 142 p129 166 v dd .pad1 196 gc12 200 p046 141 p130 165 v dd .pad2 51 k0 9 p047 140 p131 164 v dd .pad2 66 k1 8 p048 62 p132 163 v dd .pad2 76 k2 7 p049 63 p133 162 v dd .pad2 108 k3 6 p050 64 p134 161 v dd .pad2 129 k4 5 p051 65 p135 160 v dd .pad2 139 p000 199 p052 67 p136 126 v ss 42 p001 198 p053 68 p137 125 v ss 112 p002 197 p054 69 p138 124 v ss 159 p003 195 p055 70 p139 123 v ss 10 p004 194 p056 21 p140 122 v ss 20 p005 193 p057 22 p141 121 v ss 29 p006 192 p058 23 p142 120 v ss 31 p007 191 p059 24 p143 119 v ss 40 p008 157 p060 25 p144 83 v ss 52 p009 156 p061 26 p145 84 v ss 61 p010 154 p062 27 p146 85 v ss 71 p011 153 p063 28 p147 86 v ss 72 p012 152 p096 178 p148 87 v ss 82 p013 151 p097 177 p149 88 v ss 103 p014 150 p098 176 p150 89 v ss 118 p015 149 p099 175 p151 90 v ss 127 p016 53 p100 174 p152 41 v ss 137 p017 54 p101 172 p153 43 v ss 138 p018 55 p102 171 p154 44 v ss 148 p019 56 p103 170 p155 45 v ss 158 p020 57 p104 136 p156 46 v ss 169 p021 58 p105 135 p157 48 v ss 179 p022 59 p106 134 p158 49 v ss 181 p023 60 p107 133 p159 50 v ss 190 p024 11 p108 132 ra0 117 we 98 table 18. psx128b [pqfp 208l package] pinout by pin name
psx family data sheet january 2000 revision 4.0 45 8.6 psx128b [pqfp 208l package] pinout figure 41. psx128b [pqfp 208l package] pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 gc3 gc2 gc1 gc0 k4 k3 k2 k1 k0 v ss p024 p025 p026 p027 p028 p029 p030 p031 v dd .pad1 v ss p056 p057 p058 p059 p060 p061 p062 p063 v ss v dd .pad1 v ss p120 p121 p122 p123 p124 p125 p126 p127 v ss p152 v ss p153 p154 p155 p156 v dd p157 p158 p159 v dd .pad2 v ss gc4 gc5 gc6 gc7 gc8 gc9 gc10 gc11 gc12 p000 p001 p002 v dd .pad1 p003 p004 p005 p006 p007 v ss p032 p033 p034 p035 p036 p037 p038 p039 v ss v dd .pad1 v ss p096 p097 p098 p099 p100 v dd p101 p102 p103 v ss v dd .pad1 p128 p129 p130 p131 p132 p133 p134 p135 v ss v ss p008 p016 p017 p018 p019 p020 p021 p022 p023 v ss p048 p049 p050 p051 v dd .pad2 p052 p053 p054 p055 v ss v ss p112 p113 p114 v dd .pad2 p115 p116 p117 p118 p119 v ss p144 p145 p146 p147 p148 p149 p150 p151 tdo tck tdi tms trst* bank strobe we data3 data2 data1 data0 v ss ca3 p009 v dd .pad1 p010 p011 p012 p013 p014 p015 v ss p040 p041 p042 p043 p044 p045 p046 p047 v dd .pad2 v ss v ss p104 p105 p106 p107 p108 p109 p110 v dd .pad2 p111 v ss p136 p137 p138 p139 p140 p141 p142 p143 v ss ra0 ra1 ra2 ra3 ra4 v ss ra5 ra6 ra7 v dd .pad2 ca0 ca1 ca2 top view i/o ports powered by v dd .pad1 i/o ports powered by v dd .pad2
psx family data sheet 46 revision 4.0 january 2000 8.7 psx96b [pqfp 160l package] pinout by pin location pin # name pin # name pin # name pin # name 1 gc2 41 p016 81 ca2 121 p008 2 gc1 42 p017 82 ca1 122 v ss 3 gc0 43 p018 83 ca0 123 v ss 4 k4 44 p019 84 v dd .pad2 124 p135 5 k3 45 p020 85 ra7 125 p134 6 k2 46 p021 86 ra6 126 p133 7 k1 47 p022 87 ra5 127 p132 8 k0 48 p023 88 v ss 128 p131 9v ss 49 v ss 89 ra3 129 p130 10 p024 50 p048 90 ra2 130 p129 11 p025 51 p049 91 ra1 131 p128 12 p026 52 p050 92 ra0 132 v dd .pad1 13 p027 53 p051 93 v ss 133 v ss 14 p028 54 v dd .pad2 94 p143 134 p039 15 p029 55 p052 95 p142 135 p038 16 p030 56 p053 96 p141 136 p037 17 p031 57 p054 97 p140 137 p036 18 v dd .pad1 58 p055 98 p139 138 p035 19 v ss 59 v ss 99 p138 139 p034 20 p056 60 p144 100 p137 140 p033 21 p057 61 p145 101 p136 141 p032 22 p058 62 p146 102 v ss 142 v ss 23 p059 63 p147 103 v dd .pad2 143 p007 24 p060 64 p148 104 p047 144 p006 25 p061 65 p149 105 p046 145 p005 26 p062 66 p150 106 p045 146 p004 27 p063 67 p151 107 p044 147 p003 28 v ss 68 tdo 108 p043 148 v dd .pad1 29 p152 69 tck 109 p042 149 p002 30 v ss 70 tdi 110 p041 150 p001 31 p153 71 tms 111 p040 151 p000 32 p154 72 trst* 112 v ss 152 gc11 33 p155 73 bank 113 p015 153 gc10 34 p156 74 strobe 114 p014 154 gc9 35 v dd 75 we 115 p013 155 gc8 36 p157 76 data3 116 p012 156 gc7 37 p158 77 data2 117 p011 157 gc6 38 p159 78 data1 118 p010 158 gc5 39 v dd .pad2 79 data0 119 v dd .pad1 159 gc4 40 v ss 80 ca3 120 p009 160 gc3 table 19. psx96b [pqfp 160l package] pinout by pin location
psx family data sheet january 2000 revision 4.0 47 8.8 psx96b [pqfp 160l package] pinout by pin name name pin # name pin # name pin # name pin # bank 73 p014 114 p054 57 p158 37 ca0 83 p015 113 p055 58 p159 38 ca1 82 p016 41 p056 20 ra0 92 ca2 81 p017 42 p057 21 ra1 91 ca3 80 p018 43 p058 22 ra2 90 data0 79 p019 44 p059 23 ra3 89 data1 78 p020 45 p060 24 ra5 87 data2 77 p021 46 p061 25 ra6 86 data3 76 p022 47 p062 26 ra7 85 gc0 3 p023 48 p063 27 strobe 74 gc1 2 p024 10 p128 131 tck 69 gc2 1 p025 11 p129 130 tdi 70 gc3 160 p026 12 p130 129 tdo 68 gc4 159 p027 13 p131 128 tms 71 gc5 158 p028 14 p132 127 trst* 72 gc6 157 p029 15 p133 126 v dd 35 gc7 156 p030 16 p134 125 v dd .pad1 18 gc8 155 p031 17 p135 124 v dd .pad1 119 gc9 154 p032 141 p136 101 v dd .pad1 132 gc10 153 p033 140 p137 100 v dd .pad1 148 gc11 152 p034 139 p138 99 v dd .pad2 39 k0 8 p035 138 p139 98 v dd .pad2 54 k1 7 p036 137 p140 97 v dd .pad2 84 k2 6 p037 136 p141 96 v dd .pad2 103 k3 5 p038 135 p142 95 v ss 30 k4 4 p039 134 p143 94 v ss 88 p000 151 p040 111 p144 60 v ss 123 p001 150 p041 110 p145 61 v ss 9 p002 149 p042 109 p146 62 v ss 19 p003 147 p043 108 p147 63 v ss 28 p004 146 p044 107 p148 64 v ss 40 p005 145 p045 106 p149 65 v ss 49 p006 144 p046 105 p150 66 v ss 59 p007 143 p047 104 p151 67 v ss 93 p008 121 p048 50 p152 29 v ss 102 p009 120 p049 51 p153 31 v ss 112 p010 118 p050 52 p154 32 v ss 122 p011 117 p051 53 p155 33 v ss 133 p012 116 p052 55 p156 34 v ss 142 p013 115 p053 56 p157 36 we 75 table 20. psx96b [pqfp 160l package] pinout by pin name
psx family data sheet 48 revision 4.0 january 2000 8.9 psx96b [pqfp 160l package] pinout figure 42. psx96b [pqfp 160l package] pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 gc3 gc4 gc5 gc6 gc7 gc8 gc9 gc10 gc11 p000 p001 p002 v dd .pad1 p003 p004 p005 p006 p007 v ss p032 p033 p034 p035 p036 p037 p038 p039 v ss v dd .pad1 p128 p129 p130 p131 p132 p133 p134 p135 v ss v ss p008 p009 v dd .pad1 p010 p011 p012 p013 p014 p015 v ss p040 p041 p042 p043 p044 p045 p046 p047 v dd .pad2 v ss p136 p137 p138 p139 p140 p141 p142 p143 v ss ra0 ra1 ra2 ra3 v ss ra5 ra6 ra7 v dd .pad2 ca0 ca1 ca2 top view gc2 gc1 gc0 k4 k3 k2 k1 k0 v ss p024 p025 p026 p027 p028 p029 p030 p031 v dd .pad1 v ss p056 p057 p058 p059 p060 p061 p062 p063 v ss p152 v ss p153 p154 p155 p156 v dd p157 p158 p159 v dd .pad2 v ss p016 p017 p018 p019 p020 p021 p022 p023 v ss p048 p049 p050 p051 v dd .pad2 p052 p053 p054 p055 v ss p144 p145 p146 p147 p148 p149 p150 p151 tdo tck tdi tms trst* bank strobe we data3 data2 data1 data0 ca3 i/o ports powered by v dd .pad1 i/o ports powered by v dd .pad2
psx family data sheet january 2000 revision 4.0 49 9.0 m echanical s pecification 9.1 pqfp package dimensions figure 43. pqfp package dimensions package dimension table pqfp/240l pqfp/208l pqfp/160l inch mm inch mm inch mm a max 0.155 3.93 0.157 3.99 .160 4.07 a1 min 0.010 0.25 0.010 0.25 .010 0.25 max 0.017 0.43 0.017 0.43 .018 0.47 a2 min 0.130 3.30 0.135 3.43 .126 3.20 max 0.138 3.50 0.140 3.56 .142 3.60 d min 1.354 34.40 1.195 34.40 1.219 30.95 max 1.370 34.80 1.215 30.91 1.238 31.45 d1 min 1.256 31.90 1.098 27.93 1.098 27.90 max 1.264 32.10 1.106 28.14 1.106 28.10 e min 1.354 34.40 1.195 34.40 1.219 30.95 max 1.370 34.80 1.215 30.91 1.238 31.45 e1 min 1.256 31.90 1.098 27.93 1.098 27.90 max 1.264 32.10 1.106 28.14 1.106 28.10 l min 0.019 0.50 0.018 0.46 0.029 0.73 max 0.030 0.75 0.030 0.76 0.041 1.03 b min 0.007 0.17 0.006 0.15 0.009 0.22 max 0.011 0.27 0.011 0.28 0.014 0.35 e bsc. 0.0197 0.50 0.0197 0.50 0.0256 0.65 table 21. pqfp package dimensions w x detail x top view side view detail w e e1 0.10 (0.004) 0 - 7 8 - 12 l e b a1 d1 d dimension in mm. (in.) a2 a
psx family data sheet 50 revision 4.0 january 2000 10.0 p ackage t hermal r esistance note: (1) thermal performance values are based on simulation data. package pin count q jc (c/w) q ja ( c/w) still air q ja ( c/w) 200 ifpm q ja ( c/w) 400 ifpm q ja ( c/w) 600 ifpm pqfp 160 6.7 38.0 29.2 24.4 21.7 208 6.6 36.6 27.4 24.0 21.4 240 6.5 35.5 26.2 23.7 21.6 table 22. thermal resistance of psx packages
psx family data sheet january 2000 revision 4.0 51 11.0 c omponent a vailability and o rdering i nformation the following table lists the psx devices and the different package options, and speed grades that are currently available. package pins 160 208 240 type pqfp pqfp pqfp code pq160 pq208 pq240 psx160 -100 x -133 x psx128b -100 x -133 x psx96b -100 x -133 x table 23. component availability device speed package ordering# psx160 -100 pq 240 psx160-pq240 -133 pq 240 psx160-133pq240 psx128b -100 pq 208 psx128b-pq208 -133 pq 208 psx128b-133pq208 psx96b -100 pq 160 PSX96B-PQ160 -133 pq 160 psx96b-133pq160 table 24. ordering information
psx family data sheet 52 revision 4.0 january 2000 12.0 psx f amily at a g lance device psx160 psx128b psx96b number of usable i/o 160 128 96 switch matrix size 160 128 96 pin-to-pin delay (ns) 7.0 7.0 7.0 nrz data rate (mbs) 160 160 160 clock frequency (mhz) 133 133 133 bus widths (bits) number of buses 4 8 16 32 40 20 10 5 4 8 16 32 32 16 8 4 4 8 16 32 24 12 6 3 i/o current drive (ma) 16 16 16 number of general control (gc) and key control pins 13 gc 5 key 13 gc 5 key 12 gc 5 key i/o port modes in/out/bus repeater registered in/out/bidirectional latched in/out/bidirectional tristate in/out/bidirectional in/out/bus repeater registered in/out/bidirectional latched in/out/bidirectional tristate in/out/bidirectional in/out/bus repeater registered in/out/bidirectional latched in/out/bidirectional tristate in/out/bidirectional process ( m m) 0.6 0.6 0.6 core voltage (v) 5 5 5 i/o voltage (v) 3.3 and/or 5 3.3 and/or 5 3.3 and/or 5 package(s) 240 pqfp 208 pqfp 160 pqfp table 25. psx family summary
psx family data sheet january 2000 revision 4.0 53 13.0 p roduct s tatus d efinitions i-cube ? and switchset ? are registered trademarks and rapidconnect, rapidconfigure, iq, iqx, msx, stacklink, and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves t he right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product poss ible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. life support applications i-cube products are not designed for use in life support appliances, devices, or systems where malfunction of an i-cube product can reasonably be expected to result in personal injury. i-cube customers using or selling i-cube products for use in such application do so at t heir own risk and agree to fully indemnify i-cube for any damages resulting from such improper use or sale. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 56257 80, 5710550, 5717871, 5734334, 5754791, 5781717, 5784003, 5790048, 5884101. additional patents pending. psx family data sheetrevision 4.0, january 2000 previously printed as psx family data sheetrevision 3.0, january 1999 copyright ? 1992-2000 i-cube, inc. all rights reserved. unpublishedrights reserved under the copyright laws of the united stat es. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008, usa phone: +(408) 341-1888 fax: +(408) 341-1899 email: marketing@icube.com internet: http://www.icube.com psx family data sheet revision 4.0, january 2000 document # mkt-psxfamily-ds data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

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